VHDL Simulator
VHDL Simulation
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Every ALDEC simulator (Active-HDL™, Riviera-PRO™) provides full support of the IEEE 1076-1993 Standard, current IEEE 1076™-2002 VHDL (VHSIC Hardware Description Language) standard along with settings that enable compatibility with older versions of the standards as well as some features from forthcoming VHDL 2006 Standard (Draft IEEE P1076-2008/D4.2), such as VHPI interfacing to C/C++ code. For greater convenience, every ALDEC simulator is equipped with options that allow optimization of simulations for maximal speed or extensive debugging while strictly adhering to IEEE Standards.
Aldec has also created an interactive VHDL learning tool that has been used by thousands of engineers and students to quickly get familiar with VHDL design concepts and language' syntax. The Evita™ Tutorial is structured in the same way as a traditional book and is composed of chapters, sections and pages. Also, like in a book you can browse through the table of contents. The navigation buttons allow you to easily switch to any section of the tutorial. This fun innovative multimedia training is provided free of charge. |
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Verification
- VHDL Simulation
- Verilog Simulation
- SystemC
- SystemVerilog
- Assertions (PSL, SVA and OVA)
- Acceleration/Emulation
- Code Coverage
- Design Rule Checker (LINT)
Specialty Solutions
- In-Hardware Simulation
- DO-254 Compliance
- MATLAB/Simulink Co-Simulation
- Verification IP
- HDL Regression Manager
- NIOS II Co-Verification
- ARM Co-Verification
- Actel RTAX Prototyping